1. Field of the Invention
The present invention relates to a semiconductor device for use in a semiconductor memory device; and, more particularly, to an apparatus for generating a stable high voltage signal by selectively changing a delay time according to a voltage level for an external power signal.
2. Description of the Prior Art
In a typical semiconductor memory device, a high voltage signal is used for compensating a voltage loss caused due to threshold voltages of metal oxide semiconductor (MOS) transistors. The high voltage signal has a voltage level higher than an external power signal. A semiconductor device for generating the high voltage signal is called a high voltage generation circuit.
Since the high voltage signal can compensate for the voltage loss, the high voltage generation circuits are widely used in a word line drive circuit, a bit line isolation circuit, a data output buffer circuit, and the like.
FIG. 1 is a block diagram showing a conventional high voltage generation circuit.
Referring to FIG. 1, a conventional high voltage generation circuit includes a level detection unit 110, an oscillation unit 130, a control signal generation unit 150 and a voltage pump unit 170.
The level detection unit 110 detects a voltage level of a high voltage signal Vpp to generate a high voltage enable signal PPEN. The level detection unit 110 includes a high voltage level detector 111 and a delay unit 113. The high voltage level detector 111 detects the voltage level of the high voltage signal Vpp to generate a high voltage detection signal PPDET. Here, the high voltage detection signal PPDET is a signal that is activated when the high voltage signal Vpp becomes higher than a target voltage level. The delay unit 113 delays the high voltage detection signal PPDET for a predetermined time to generate the high voltage enable signal PPEN.
The oscillation unit 130 generates an oscillation signal OSC in response to the high voltage enable signal PPEN. That is, if the high voltage signal Vpp reaches the target voltage level, the high voltage enable signal PPEN is activated to a high level so that the oscillation unit 130 stops an oscillating operation. If the high voltage signal Vpp becomes less than the target voltage level, the high voltage enable signal PPEN is inactivated to a low level so that the oscillation unit 130 starts the oscillating operation.
The control signal generation unit 150 generates a control signal CTRL in response to the oscillation signal OSC.
The voltage pump unit 170 increases a voltage level of the external power signal Vext through a pumping operation in response to the control signal CTRL, to thereby generate the high voltage signal Vpp. Here, the high voltage signal Vpp is feedback to the level detection unit 110.
FIG. 2 is a timing chart for explaining an operation of a conventional high voltage generation circuit.
Referring to FIG. 2, if the external power signal Vext reaches the target voltage level, the high voltage detection signal is activated to a high level, and, after a predetermined delay time, the high voltage enable signal PPEN is activated to a high level. The oscillation signal OSC is disabled to a low level so that the voltage pump unit 170 stops the pumping operation. As a result, the voltage level of the high voltage signal Vpp gradually decreases.
Then, if the voltage level of the high voltage signal Vpp becomes less than the target voltage level, the high voltage enable signal PPEN is inactivated to a low level, thereby starting the oscillation unit 130. As a result, the voltage pump unit 170 performs the pumping operation so that the voltage level of the high voltage signal Vpp is gradually increased.
However, since the delay unit 113 has a fixed delay time, the voltage pump unit 170 increases the voltage level of the high voltage signal Vpp as much as a predetermined voltage level without any consideration of the voltage level of the external power signal Vext. Thus, even when the external power signal Vext has a relatively high level, the voltage pump unit 170 performs the pumping operation for a period corresponding to the delay time that is determined by the delay unit 113. As a result, the high voltage signal Vpp is increased to an extremely high voltage level. Therefore, a reliability of the semiconductor device is degraded and an erroneous operation may be caused.
It is, therefore, an object of the present invention to provide an apparatus for generating a stable high voltage signal by selectively changing a delay time according to a voltage level of an external power signal.
In accordance with an aspect of the present invention, there is provided an apparatus for generating a high voltage signal, comprising: a voltage pump means for increasing a voltage level of an external power signal in response to a control signal; a level detection means for detecting a voltage level of the high voltage signal and delaying the high voltage signal for a predetermined delay time to generate a high voltage enable signal, wherein the predetermined delay time is determined according to a voltage level of the external power signal; an oscillation means for performing an oscillating operation in response to the high voltage enable signal and generating an oscillation signal; and a control signal generation means for generating the control signal in response to the oscillation signal.
The level detection means includes: a high voltage level detection means for detecting the high voltage signal and generating a high voltage detection signal when the voltage level of the high voltage becomes higher than a predetermined target voltage level; an external power level detection means for detecting the external voltage signal and generating an external voltage detection signal when the voltage level of the external voltage level becomes less than a predetermined voltage level; and a delay means for delaying the high voltage detection signal for the predetermined delay time according to the external power detection signal.